1. Field of the Invention
The present invention relates to a nitride semiconductor substrate comprising a group 13 nitride and used suitably for a semiconductor power device which withstands a high voltage.
2. Description of the Related Art
Group 13 nitride semiconductors including GaN attract attention as next-generation semiconductor power device materials. In particular, a nitride semiconductor substrate having grown group 13 nitride semiconductor crystal epitaxially on a substrate of different materials, such as sapphire, silicon, etc., has many advantages in respect of the balance between a device property and manufacturing cost. Especially, one that uses a Si single crystal substrate which allows a diameter of 6 inches is very useful industrially.
However, since a nitride semiconductor has a thermal expansion coefficient larger than that of a Si single crystal, a nitride semiconductor layer epitaxially grown on a Si single crystal substrate at a high temperature may generate a crack, a crystal defect due to difference in crystal-lattice constant from Si when it is cooled to room temperature.
To cope with this, improvements have occurred, such as using a highly concentrated doped Si substrate when depositing a nitride semiconductor layer, preparing a buffer layer on the Si substrate, etc. Further, in order to form a good buffer layer, Japanese Patent Application Publication No. 2003-59948 (Patent Literature 1), for example, has proposed a plane direction is arranged such that the principal plane of the Si single crystal substrate on which a buffer layer is deposited is flush with a (111) plane or inclined at an angle in the range of ±4° to the (111) plane.
Furthermore, Japanese Patent Application Publication No. 2012-15304 (Patent Literature 2) discloses that, in contact with the principal plane of the Si substrate whose principal plane is a plane inclined at an offset angle of 0.1° or less to the (111) plane, an AlN layer whose half-value width of a rocking curve by X-ray diffraction at (002) plane is 2000 sec or less is prepared, on which a GaN type semiconductor layer is provided, whereby crystallinity of the nitride semiconductor can be improved and the property of the semiconductor device can also be improved.
As described in Patent Literature 2 above, it is known that the offset angle of the Si substrate principal plane influences the crystallinity and evenness of the nitride semiconductor layer which is deposited and formed on the principal plane.
Further, Patent Literature 1 above discloses that the plane direction of the Si single crystal substrate and inclination (offset angle) are specified for the purpose of reducing atomic steps on a crystal surface of the buffer layer and a semiconductor region, thus some steps are less problematic in the case where an epitaxial growth layer is comparatively thick,
Incidentally, in recent years, power devices, such as a high-electron mobility transistor (HEMI) element, have been requiring a high withstand voltage, so as to bear even a voltage exceeding 600V. In such a high withstand voltage device, the nitride layer requires the total thickness of greater than 4 μm.
Therefore, in such a thick nitride layer, in order to attain reduction (i.e., improvement in evenness) of the step of the nitride layer surface, it is thought that it is not necessary to employ the Si single crystal substrate with a plane direction in which an offset angle is comparatively small as described above in Patent Literatures 1 and 2.
However, when the nitride layer is thickened as described above, there arises a problem in that the cracks and warp are generated in the nitride semiconductor substrate in the case of epitaxial growth. In particular, the diameter of the substrate has been enlarged for improving the manufacture efficiency in recent years, 6 inch substrates have been manufactured, and it becomes progressively more difficult to control the warp in such a large diameter substrate.
Such problems are conventionally addressed by reducing stress by means of a multilayered buffer layer, by a method of restricting dislocation generation, or by a method of controlling the warp of the whole substrate by controlling impurity concentration of the Si single crystal substrate of a base. However, even in the case where such technology is applied, it is very difficult to restrict the warp in the large diameter substrate.
Then, the present inventors have diligently repeated various examinations of the substrates having the above-described thick buffer layer for high withstand voltage power devices. Thus, we have found that the warp of the nitride semiconductor substrate and generation of cracks can be controlled effectively, while maintaining good crystallinity, by a suitable combination of a specific underside form, a bulk property, and a surface offset angle in the Si single crystal substrate.